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4 April 2024
- 15:3015:30, 4 April 2024 diff hist +98 N BAYWIRES Created page with " * [https://www.every.org/hacker-dojo/f/baywires-experimenta BAYWIRES by DEFAULT (via every.org)]"
2 January 2024
- 01:0401:04, 2 January 2024 diff hist +43 N User talk:Wikiadmin Created page with "<strike>password password password</strike>" current
- 00:5800:58, 2 January 2024 diff hist +178 N User:QSV di di di dahhhh
- 00:5100:51, 2 January 2024 diff hist +46 m QSV vertical sync
- 00:4900:49, 2 January 2024 diff hist +368 m QSV bright idear from QSV lunch ..._ ..._ ..._
- 00:3900:39, 2 January 2024 diff hist +39 m File:Lawn-Tennis-Vertical-Sync.png attribution -> Dr. Hugo current
- 00:3600:36, 2 January 2024 diff hist +742 N File:Lawn-Tennis-Vertical-Sync.png The vertical sync circuit is the same configuration as the horizontal sync system, except the drive pulse is the HRESET pulse, not the master clock or CLK. During counting after 256 counts this sets pin 5 (the 256V connection) of D9 high, then after another 1 + 4 = 261 counts to satisfy the inputs of the 7410 NAND gate D8, the output of D8 falls low. Then on the 262nd HRESET pulse the counters are reset. The division of the horizontal rate is therefore is 262. HRESET has a frequency of 15,7...