File:Lawn-Tennis-Vertical-Sync.png: Revision history

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2 January 2024

  • curprev 00:3600:36, 2 January 2024‎ Wikiadmin talk contribs‎ 742 bytes +742‎ The vertical sync circuit is the same configuration as the horizontal sync system, except the drive pulse is the HRESET pulse, not the master clock or CLK. During counting after 256 counts this sets pin 5 (the 256V connection) of D9 high, then after another 1 + 4 = 261 counts to satisfy the inputs of the 7410 NAND gate D8, the output of D8 falls low. Then on the 262nd HRESET pulse the counters are reset. The division of the horizontal rate is therefore is 262. HRESET has a frequency of 15,7...
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