View source for File:Lawn-Tennis-Vertical-Sync.png

== Summary ==
The vertical sync circuit is the same configuration as the horizontal sync
system, except the drive pulse is the HRESET pulse, not the master
clock or CLK.

During counting after 256 counts this sets pin 5 (the 256V connection)
of D9 high, then after another 1 + 4 = 261 counts to satisfy the inputs of
the 7410 NAND gate D8, the output of D8 falls low. Then on the 262nd
HRESET pulse the counters are reset.

The division of the horizontal rate is therefore is 262. HRESET has a
frequency of 15,731 Hz, so VRESET has a frequency of 15731/262 =
60.04 Hz which is the Field frequency for the monitor or very close to it.
The horizontal and vertical sync pulses are mixed together by the XOR
gate A4 to become (not)composite sync.